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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. drv8847 slvse65 ? july 2018 drv8847 dual h-bridge motor driver 1 1 features 1 ? dual h-bridge motor driver ? single or dual brushed dc motors ? one bipolar stepper motor ? solenoid loads ? 2.7-v to 18-v operating voltage range ? high output current per h-bridge ? 1-a rms driver current at t a = 25 c ? 2-a rms driver current in parallel mode at t a = 25 c ? low on-state resistance ? 1000-m r ds(on) (hs + ls) at t a = 25 c ? simple control interface options ? 4-pin interface ? 2-pin interface ? parallel bridge interface ? independent bridge interface ? current regulation with 20- s fixed off time ? torque scalar for scaling output current to 50% ? supports 1.8-v, 3.3-v, 5-v logic inputs ? low-power sleep mode ? 3- a sleep mode supply current ? i 2 c device variant available (drv8847s) ? detailed diagnostics on i 2 c registers ? multi-slave operation support ? supports standard and fast i 2 c mode ? small packages and footprints ? 16 pin tssop (no thermal pad) ? 16 pin htssop powerpad ? package ? 16 pin wqfn thermal package ? built-in protection features ? vm undervoltage lockout (uvlo) ? overcurrent protection (ocp) ? open load detection (old) ? thermal shutdown (tsd) ? fault condition indication pin (nfault) 2 applications ? refrigerator damper and ice maker ? washers, dryers and dishwashers ? electronic point-of-sale (epos) printers ? stage lighting equipment ? miniature circuit breakers and smart meters 3 description the drv8847 device is a dual h-bridge motor driver for industrial applications, home appliances, epos printers, and other mechatronic applications. this device can be used for driving two dc motors, a bipolar stepper motor, or other loads such as relays. a simple pwm interface allows easy interface with the controller. the drv8847 device operates off a single power supply and supports a wide input supply range from 2.7 to 18 v. the output stage of the driver consists of n-channel power mosfets configured as two full h-bridges to drive motor windings or four independent half bridges (in independent bridge interface). a fixed off time controls the peak current in the bridge which can drive a 1-a load (2-a in parallel mode with proper heat sinking, at 25 c t a ). a low-power sleep mode is provided to achieve a low quiescent current draw by shutting down much of the internal circuitry. additionally, a torque scalar is provided which dynamically scales the output current through a digital input pin. this feature lets the controller decrease the current required for lower power consumption. internal protection functions are provided for undervoltage-lockout, overcurrent protection on each fet, short circuit protection, open-load detection, and overtemperature. fault conditions are indicated by on the nfault pin. the i 2 c device variant (drv8847s) has detailed diagnostics. device information (1) part number package body size (nom) drv8847 htssop (16) 5.00 mm 6.40 mm tssop (16) 5.00 mm 6.40 mm wqfn (16) 3.00 mm 3.00 mm drv8847s tssop (16) 5.00 mm 6.40 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic 1 a 1 a stepper 2.7 to 18 v drv8847 dual h-bridge driver inx trq nfault nsleep built-in protection controller mode current regulation advance information tools & software technical documents ordernow productfolder support &community
2 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 i2c timing requirements ......................................... 7 7 detailed description ............................................ 10 7.1 overview ................................................................. 10 7.2 functional block diagram ....................................... 11 7.3 feature description ................................................. 13 7.4 device functional modes ........................................ 31 7.5 programming ........................................................... 33 7.6 register map ........................................................... 35 8 application and implementation ........................ 40 8.1 application information ............................................ 40 8.2 typical application ................................................. 40 9 power supply recommendations ...................... 44 9.1 bulk capacitance sizing ......................................... 44 10 layout ................................................................... 45 10.1 layout guidelines ................................................. 45 10.2 layout example .................................................... 45 10.3 thermal considerations ........................................ 46 10.4 power dissipation ................................................. 46 11 device and documentation support ................. 47 11.1 documentation support ........................................ 47 11.2 receiving notification of documentation updates 47 11.3 community resources .......................................... 47 11.4 trademarks ........................................................... 47 11.5 electrostatic discharge caution ............................ 47 11.6 glossary ................................................................ 47 12 mechanical, packaging, and orderable information ........................................................... 47 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes july 2018 * initial release. advance information
3 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions drv8847 pw package 16-pin tssop top view drv8847 pwp powerpad ? package 16-pin htssop top view drv8847 rte package 16-pin wqfn with exposed thermal pad top view drv8847s pw package 16-pin tssop top view 1 nsleep 16 in1 2 out1 15 in2 3 isen12 14 mode 4 out2 13 gnd 5 out4 12 vm 6 isen34 11 trq 7 out3 10 in4 8 nfault 9 in3 not to scale thermal pad advance information 1 nsleep 16 in1 2 out1 15 in2 3 isen12 14 mode 4 out2 13 gnd 5 out4 12 vm 6 isen34 11 trq 7 out3 10 in4 8 nfault 9 in3 not to scale 1 nsleep 16 in1 2 out1 15 in2 3 isen12 14 sda 4 out2 13 gnd 5 out4 12 vm 6 isen34 11 scl 7 out3 10 in4 8 nfault 9 in3 not to scale 16 out1 5 out3 1 isen12 12 mode 15 nsleep 6 nfault 2 out2 11 gnd 14 in1 7 in3 3 out4 10 vm 13 in2 8 in4 4 isen34 9 trq not to scale thermal pad
4 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) i = input, o = output, od = open-drain output, pwr = power pin functions pin type (1) description name drv8847 drv8847s tssop htssop wqfn tssop gnd 13 11 13 pwr device ground. both the gnd pin and device thermal pad (htssop and wqfn packages) must be connected to ground in1 16 14 16 i half-bridge input 1 in2 15 13 15 i half-bridge input 2 in3 9 7 9 i half-bridge input 3 in4 10 8 10 i half-bridge input 4 isen12 3 1 3 o full-bridge-12 sense. connect this pin to the current sense resistor for full- bridge-12. connect this pin to the gnd pin if current regulation is not required. isen34 6 4 6 o full-bridge-34 sense. connect this pin to the to current sense resistor for full-bridge-34. connect this pin to the gnd pin if current regulation is not required. mode 14 12 ? i tri-state pin for selection of driver operating mode nfault 8 6 8 od fault indication pin. this pin is pulled logic low with a fault condition. this open-drain output requires an external pullup resistor. nsleep 1 15 1 i sleep mode input. set this pin to logic high to enable the device. set this pin to logic low to go to low-power sleep mode out1 2 16 2 o half-bridge output 1 out2 4 2 4 o half-bridge output 2 out3 7 5 7 o half-bridge output 3 out4 5 3 5 o half-bridge output 4 scl ? ? 11 i i 2 c clock signal. sda ? ? 14 od i 2 c data signal. the sda pin requires a pullup resistor. trq 11 9 ? i torque current scalar vm 12 10 12 pwr power supply. connect the vm pin to the motor power supply. bypass this pin to ground with a vm-rated 0.1- f and 10- f (minimum) ceramic capacitor. advance information
5 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating condition . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating ambient temperature range (unless otherwise noted) (1) min max unit power supply pin voltage (vm) -0.3 20 v power supply voltage ramp rate (vm) 0 2 v/ s digital pin voltage (in1, in2, in3, in4, trq, nsleep, nfault, scl, sda) -0.3 5.5 v continuous phase node pin voltage (out1, out2, out3, out4) -0.7 vm + 0.6 v continuous shunt amplifier input pin voltage (isen12, isen34) -0.6 0.6 v peak drive current (out1, out2, out3, out4) internally limited a ambient temperature, t a -40 125 c junction temperature, t j -40 150 c storage temperature, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 (1) errata: the current silicon is functional from 2.7-v to 15-v (2) power dissipation and thermal limits must be observed (3) errata: the current silicon is functional from 0 c to 85 c (ambient temperature) 6.3 recommended operating conditions over operating ambient temperature range (unless otherwise noted) min nom max unit v vm power supply voltage (vm) 2.7 18 (1) v v in logic input voltage (in1, in2, in3, in4, trq, nsleep, scl, sda) 0 5 v i rms motor rms current per bridge (out1, out2, out3, out4) 0 1 (2) a f pwm pwm frequency (in1, in2, in3, in4) 0 250 (2) khz v od open drain pullup voltage (nfault) 0 5 v i od open drain output current (nfault) 0 5 ma t a operating ambient temperature -40 (3) 85 c t j operating junction temperature -40 150 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) drv8847, drv8847s drv8847 drv8847 unit pw (tssop) pwp (htssop) rte (qfn) 16 pins 16 pins 16 pins r ja junction-to-ambient thermal resistance 107.9 46.5 46.4 c/w r jc(top) junction-to-case (top) thermal resistance 38.5 40.1 47.5 c/w r jb junction-to-board thermal resistance 54.2 18.8 21.2 c/w jt junction-to-top characterization parameter 3.1 1.3 0.9 c/w advance information
6 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated thermal information (continued) thermal metric (1) drv8847, drv8847s drv8847 drv8847 unit pw (tssop) pwp (htssop) rte (qfn) 16 pins 16 pins 16 pins jb junction-to-board characterization parameter 53.6 19.0 21.3 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a 5.9 6.1 c/w 6.5 electrical characteristics v vm = 2.7 to 18 v over operating ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit power supplies (vm) v vm vm operating voltage 2.7 18 v i vm vm operating supply current vm = 2.7 v; nsleep = 1; inx = 0 2 2.5 ma vm = 5 v; nsleep = 1; inx = 0 3 3.5 ma vm = 12 v; nsleep = 1; inx = 0 3 3.5 ma i vmq vm sleep mode current vm = 2.7 v; nsleep = 0; ta = 25 c 0.5 a vm = 2.7 v; nsleep = 0; ta = 85 c 1 a vm = 5 v; nsleep = 0; ta = 25 c 1 a vm = 5 v; nsleep = 0; ta = 85 c 1.5 a vm = 12 v; nsleep = 0; ta = 25 c 3 a vm = 12 v; nsleep = 0; ta = 85 c 3.5 a t sleep sleep time nsleep = 0 to sleep mode 2 s t wake wake-up time nsleep = 1 to output transition 1.5 ms t on turnon-time vm > uvlo to output transition (nsleep = 1) 1.5 ms logic-level inputs (in1, in2, in3, in4, nsleep, trq, scl, sda) v il input logic low voltage 0 0.6 v v ih input logic high voltage 1.6 5.5 v v hys input logic hysteresis nsleep pin 40 mv v hys input logic hysteresis in1, in2, in3, in4, trq, scl pins 100 mv i il input logic low current v in = 0 v -1 1 a i ih input logic high current in1, in2, in3, in4, trq, v in = 5 v 1 35 a nsleep, v in = 5 v 1 25 a t pd propagation delay inx edge to output 100 400 600 ns tri-level inputs (mode) v il tri-level input logic low voltage 0 0.6 v v iz tri-level input hi-z voltage 1.2 v v ih tri-level input logic high voltage 1.6 5.5 v i il tri-level input logic low current v in = 0 v 1 35 a i ih tri-level input logic high current v in = 5 v 1 35 a open-drain outputs (nfault) v ol output logic low voltage i od = 5 ma 0.5 v i oh output logic high current v od = 3.3 v -1 1 a open-drain outputs (sda) v ol output logic low voltage i od = 5 ma 0.5 v i oh output logic high current v od = 3.3 v -1 1 a c b capacitive load for each bus line 400 pf driver outputs (out1, out2, out3, out4) advance information
7 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) v vm = 2.7 to 18 v over operating ambient temperature range (unless otherwise noted) parameter test conditions min typ max unit r ds(on)_hs high-side mosfet on resistance v vm = 2.7 v; i out = 0.5 a; t a = 25 c 690 800 m v vm = 2.7 v; i out = 0.5 a; t a = 85 c 950 m v vm = 5 v; i out = 0.5 a; t a = 25 c 530 620 m v vm = 5 v; i out = 0.5 a; t a = 85 c 740 m v vm = 12 v; i out = 0.5 a; t a = 25 c 520 600 m v vm = 12 v; i out = 0.5 a; t a = 85 c 700 m r ds(on)_ls low-side mosfet on resistance v vm = 2.7 v; i out = 0.5 a; t a = 25 c 570 670 m v vm = 2.7 v; i out = 0.5 a; t a = 85 c 900 m v vm = 5 v; i out = 0.5 a; t a = 25 c 460 520 m v vm = 5 v; i out = 0.5 a; t a = 85 c 690 m v vm = 12 v; i out = 0.5 a; t a = 25 c 450 520 m v vm = 12 v; i out = 0.5 a; t a = 85 c 680 m i off off-state leakage current v vm = 5 v; t j = 25 c; v out = 0 v -1 1 a t rise output rise time v vm = 12 v; i out = 0.5 a 150 ns t fall output fall time v vm = 12 v, i out = 0.5 a 150 ns t dead output dead time internal dead time 200 ns v sd body diode forward voltage i out = 0.5 a 1.1 v pwm current control (isen12, sen34) v trip isenxx trip voltage torque at 100% (trq = 0) 135 150 165 mv torque at 50% (trq = 1) 63.75 75 86.25 mv t blank current sense blanking time 1.8 s t off current control constant off time 20 s protection circuits v uvlo supply undervoltage lockout supply rising 2.7 v supply falling 2.4 v v uvlo_hys supply undervoltage hysteresis rising to falling theshold 50 mv t uvlo supply undervoltage deglitch time vm falling; uvlo report 10 s i ocp overcurrent protection trip point 2 a t ocp overcurrent protection deglitch time v vm = 12 v 3 s t retry overcurrent protection retry time 1 ms i ol open load pull up and pull down current < 15 nf on outx pin 200 a v ol open load detect threshold voltage 1 v t tsd thermal shutdown temperature 150 160 180 c t hys thermal shutdown hysteresis 40 c 6.6 i2c timing requirements min nom max unit standard mode f scl scl clock frequency 0 100 khz t hd,sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4 s t low low period of the scl clock 4.7 s t high high period of the scl clock 4 s t su,sta setup time for a repeated start condition 4.7 s t hd,dat data hold time: for i2c bus devices 0 3.45 s t su,dat data set-up time 250 ns advance information
8 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated i2c timing requirements (continued) min nom max unit t r sda and scl rise time 1000 ns t f sda and scl fall time 300 ns t su,sto set-up time for stop condition 4 s t buf bus free time between a stop and start condition 4.7 s fast mode f scl scl clock frequency 0 400 khz t hd,sta hold time (repeated) start condition. after this period, the first clock pulse is generated 0.6 s t low low period of the scl clock 1.3 s t high high period of the scl clock 0.6 s t su,sta setup time for a repeated start condition 0.6 s t hd,dat data hold time: for i2c bus devices 0 0.9 s t su,dat data set-up time 250 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t su,sto set-up time for stop condition 0.6 s t buf bus free time between a stop and start condition 1.3 s t sp pulse width of spikes to be supressed by input noise filter 50 ns figure 1. timing diagram z z z z xin1 xin2 xout1 xout2 t pd t pd t pd t pd 10% 90% 10% 90% t rise t fall advance information
9 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 2. i 2 c timing diagram sda t buf sto sta t hd,sta t low t high t r t f t hd,dat t su,dat t su,sta t hd,sta sta sto scl t su,sto advance information
10 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the drv8847 device is an integrated 2.7- to 18-v dual motor driver for industrial brushed and stepper motor applications. this driver can drive two dc motors, a bipolar stepper motor, or the solenoid loads. the device integrates two h-bridges that use nmos low-side and high-side drivers and current-sense regulation circuitry. the drv8847 device supports a high output current of 1-a rms per h-bridge using low-r ds(on) integrated mosfets. a simple pwm interface option allows easy interfacing to the h-bridge outputs. the interface options can be configured using the mode and in3 pins in the drv8847 device. the interface options can be configured through a i 2 c interface in the i 2 c device variant (drv8847s). the current regulation uses a fixed off-time (t off ) pwm scheme. the trip point for current regulation is controlled by the value of the sense resistor and fixed internal v trip value. a low-power sleep mode is included which lets the system save power when not driving the motor. the drv8847 device is available in three different packages: ? 16-pin tssop (no thermal pad) ? 16 pin htssop (powerpad) ? 16 pin wqfn (thermal pad) the i 2 c variant of the drv447 device is also available for a detailed diagnostics requirement and multi-slave operation with multi-slave operation control over i 2 c bus. the drv8847s device variant is available in one package which is the 16-pin tssop (no thermal pad). the drv8847 device has a broad range of integrated protection features. these features include power-supply undervoltage lockout, open-load detection, overcurrent faults, and thermal shutdown. advance information
11 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.2 functional block diagram figure 3. block diagram for drv8847 power internal reference and regulators overtemperature vm vm bulk 0.1 f vm gate drive and ocp isen out2 out1 out4 out3 stepper motor dc motor dc motor vm vm gate drive and ocp isen vm ppad gnd logic charge pump mode trq nsleep in1 in2 in3 output nfault v ext r sense34 (optional) isens34 r sense 12 (optional ) isens12 in4 r nfault c vm1 c vm2 advance information
12 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated functional block diagram (continued) figure 4. block diagram for drv8847s power internal reference and regulators overtemperature vm vm bulk 0.1 f vm gate drive and ocp isen aout2 aout1 bout2 bout1 stepper motor dc motor dc motor vm vm gate drive and ocp isen vm ppad gnd logic charge pump nsleep in1 in2 in3 output nfault v ext r sense34 (optional) isens34 r sense 12 (optional ) isens12 in4 i 2 c registers sda v ext scl r sda c vm1 c vm2 r nfault advance information
13 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) vext is not a pin on the drv8847 device, but a pullup resistor on the vext external supply voltage is required for the open-drain output, nfault. 7.3 feature description table 1 lists the recommended values of the external components for the gate driver. table 1. drv8847 external components component pin 1 pin 2 recommended c vm1 vm gnd 10- f (minimum) vm-rated ceramic capacitor c vm2 vm gnd 0.1- f vm-rated ceramic capacitor r nfault vext (1) nfault > 1 k ? r isen12 isen12 gnd sense resistor, see the typical application for sizing r isen34 isen34 gnd sense resistor, see the typical application for sizing 7.3.1 pwm motor drivers the drv8847 device has two identical h-bridge motor drivers with current-control pwm circuitry. figure 5 shows a block diagram of the circuitry. the two h-bridges can also be used as four independent half-bridges depending upon the interface option. the isenxx pin can be only used together with two half-bridges. figure 5. pwm motor driver circuitry advance information out2 out1 stepper motor vm pwm in1 predrive vm r sense12 isen12 + in2 ref (v trip )
14 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.2 bridge operation the full-bridge can operate in four different operating modes: forward, reverse, coast (fast decay), and brake (slow decay) operation. 7.3.2.1 forward operation this operating mode refers to the forward rotation of the motor such that the current flows from terminal a (out1 or out3) to terminal b (out2 or out4) as shown in figure 6 . in this mode, terminal a is connected to vm and terminal b is connected to ground. figure 6. forward operation 7.3.2.2 reverse operation this operating mode refers to the reverse rotation of the motor such that the current flows from terminal b (out2 or out4) to terminal a (out1 or out3) as shown in figure 7 . in this mode, terminal a is connected to ground and terminal b is connected to vm. figure 7. reverse operation advance information vm a b vm a b
15 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.2.3 coast operation (fast decay) in this operating mode, all the fets of the full-bridges are in the high impedance (hi-z) state. the motor also goes to the hi-z state, and the motor starts coasting. this operating mode also helps to decay the motor current faster and is therefore also referred to as a fast decay mode. if the motor was initially connected in forward operation (current flows from terminal a to terminal b) and if the coast operation is applied, then, because of the inductive nature of motor load, the current continues to flow in the same direction (a to b), and the anti-parallel diodes of the alternate fets starts conducting as shown in figure 8 . this flow of current through anti-parallel diodes lets the current decrease rapidly because of the higher negative potential created by the supply voltage, vm. figure 8. coast operation (fast decay) 7.3.2.4 brake operation (slow decay) this operating mode is realized by switching on both of the low-side fets of the full-bridge as shown in figure 9 . a current circulation path is provided when both low-side fets are turned on. due to this circulation path, the current decays to ground using the resistance of the motor and of the low-side fet. because this current decay is less when compared to the coast operation because of the low potential difference, this mode is also referred to the slow decay mode. figure 9. brake operation (slow decay) advance information vm a b vm a b
16 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.3 bridge control the drv8847 device can be configured in four different operating modes depending on user requirements. the mode and in3 pins are used to configure the drv8847 in one of the four different interfaces: 4-pin interface, 2- pin interface, a parallel bridge interface, and the independent bridge interface. mode selection is done using the i 2 c registers in the drv8847s device variant (see the programming section). table 2 lists the configurations to select the operating mode of the bridges. table 2. bridge mode selection (drv8847 hardware device variant) nsleep mode in3 interface 0 x x sleep mode 1 0 x 4-pin interface 1 1 0 2-pin interface 1 1 1 parallel bridge interface 1 z x independent bridge interface note the mode pin is not latched during driver operation. therefore, ti does not recommend connecting this pin to a controller to use at any time. 7.3.3.1 4-pin interface in the 4-pin interface, the drv8847 device is configured to drive a stepper motor or two bdc motors with fully functional modes. to configure 4-pin interface operation, connect the mode pin to ground and use the in1, in2, in3, and in4 pins to control the drivers. in this mode, the stepper or brushed dc motor can operate with all four modes (forward, reverse, coast, and brake mode) and the stepper motor can operate in either full-stepping mode or the non-circulating half-stepping mode. sense resistors can be connected to the isen12 and isen34 pins for independent current regulation in bridge-12 and bridge-34 respectively. use this interface option for the following loads: ? stepper motor in full-stepping mode (with or without current regulation) ? stepper motor in half-stepping mode (with or without current regulation) ? single or dual bdc motor (with or without current regulation) with full functional bdc modes (forward, reverse, brake, and coast mode) table 3 lists the configurations for 4-pin interface operation and figure 10 shows the application diagram for 4- pin interface operation. table 3. 4-pin interface (mode = 0) nsleep in1 in2 in3 in4 out1 out2 out3 out4 function (dc motor) 0 x x x x z z z z sleep mode 1 0 0 z z motor coast (fast decay) 1 0 1 l h reverse direction 1 1 0 h l forward direction 1 1 1 l l motor brake (slow decay) 1 0 0 z z motor coast (fast decay) 1 0 1 l h reverse direction 1 1 0 h l forward direction 1 1 1 l l motor brake (slow decay) advance information
17 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 10. 4-pin interface operation 7.3.3.2 2-pin interface in the 2-pin interface, the drv8847 device is configured to drive a stepper motor or two bdc motors with lower number of control inputs from micro-controller. to configure 2-pin interface operation, connect the mode pin to the external supply (3.3 v or 5 v), connect the in3 pin to ground, and use the in1 and in2 pins to control the driver. in this mode, the stepper or brushed dc motor operate in only two modes (forward mode and reverse mode) i.e. only full-step operation is supported for stepper motor. this 2-pin interface is very useful for low gpio applications such as refrigerator dampers. sense resistors can be connected to the isen12 and isen34 pins for current regulation. use this interface option for the following loads: ? stepper motor in full stepping mode (with or without current regulation) ? single or dual bdc motor (with or without current regulation) with reduced functional bdc modes (forward and reverse mode only) advance information logic vm gate drive and ocp isen mode in3 in4 nsleep vm vm gate drive and ocp isen vm controller in1 in2 gnd out2 out1 out4 out3 stepper motor dc motor dc motor r sense ( optional) isen34 r sense (optional ) isen12
18 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated table 4 lists the configurations for 2-pin interface operation and figure 11 shows the application diagram for 2- pin interface operation. table 4. 2-pin interface (mode = 1, in3 = 0) nsleep in1 in2 in3 in4 out1 out2 out3 out4 function (dc motor) 0 x x x x z z z z sleep mode 1 0 0 x l h reverse direction 1 1 0 x h l forward direction 1 0 0 x l h reverse direction 1 1 0 x h l forward direction figure 11. 2-pin interface operation logic vm gate drive and ocp isen vm vm gate drive and ocp isen vm gnd out2 out1 out4 out3 stepper motor dc motor dc motor r sense ( optional) isen34 r sense (optional ) isen12 vext in4 mode in1 in2 nsleep controller in3 'rq?w&duh advance information
19 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated note in this mode, two of the outx pins are always 'on' if the device is in non-sleep state (nsleep = high). therefore, to completely de-energize the motor-coils connected to outx pins, the user has to pull-down nsleep pin. 7.3.3.3 parallel bridge interface in the parallel bridge interface, the drv8847 device is configured to drive a higher current bdc motor by using the driver in parallel to deliver twice the motor current. to go to parallel bridge interface operation, connect the mode and in3 pins to the external supply (3.3 v or 5 v) and use the in1 and in2 pins to control the driver. this mode can deliver the full functionality of the bdc motor control with all four modes (forward, reverse, coast, and brake mode). use this interface option for the following loads: ? one high current bdc motor (with or without current regulation) with full functional bdc modes (forward, reverse, brake, and coast mode) ? two independent bdc motors operating together (with or without current regulation) with full functional bdc modes (forward, reverse, brake, and coast mode) table 5 lists the configurations for parallel bridge interface operation, and figure 12 shows the application diagram for parallel bridge interface operation. table 5. parallel interface (mode = 1, in3 = 1) nsleep in1 in2 in3 in4 out1 out2 out3 out4 function (dc motor) 0 x x x x z z z z sleep mode 1 0 0 1 x z z z z motor coast (fast decay) 1 0 1 1 x l h l h reverse direction 1 1 0 1 x h l h l forward direction 1 1 1 1 x l l l l motor brake (slow decay) note errata: parallel bridge mode is not functional with the current regulation using rsense resistor and might see some over-currents on the outx nodes. this will be fixed in next silicon revision. advance information
20 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 12. parallel mode operation 7.3.3.4 independent bridge interface in the independent bridge interface, the drv8847 device is configured for independent half-bridge operation. to configure independent bridge interface operation, leave the mode pin unconnected (hi-z state) and use the in1, in2, in3, and in4 pins to independently control the out1, out2, out3, and out4 pins respectively. only two output states of the outx pin can be controlled (either connected to vm or connected to gnd). this mode is used to drive independent loads such as relays and solenoids. use this interface option for the following loads: ? relay or solenoid coils connected to the vm pin or ground ? single or dual bdc motor (with or without current regulation) with three functional bdc modes (forward, reverse, and braking mode only) ? stepper motor in full-stepping mode (with or without current regulation) ? stepper motor in half-stepping mode (with or without current regulation) using brake mode advance information isen34 logic vm gate drive and ocp isen out2 out1 out4 out3 dc motor in4 mode in1 in2 nsleep isen12 r sense (optional) vm vm gate drive and ocp isen vm controller in3 vext 'rq?w&duh
21 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated table 6 lists the configurations for independent bridge interface operation and figure 13 shows the application diagram for independent bridge interface operation. table 6. independent bridge interface (mode = hi-z) nsleep in1 in2 in3 in4 out1 out2 out3 out4 function (dc motor) 0 x x x x z z z z sleep mode 1 0 l out1 connected to gnd 1 1 h out1 connected to vm 1 0 l out2 connected to gnd 1 1 h out2 connected to vm 1 0 l out3 connected to gnd 1 1 h out3 connected to vm 1 0 l out4 connected to gnd 1 1 h out4 connected to vm advance information
22 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 13. independent bridge interface 7.3.4 current regulation the current through the motor windings is regulated by a fixed off-time pwm current regulation circuit. with brushed dc motors, current regulation can be used to limit the stall current (which is also the start-up current) of the motor. current regulation works as follows: when an h-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and inductance of the winding. if the current reaches the current trip threshold, the bridge disables the current for a time t off before starting the next pwm cycle. note immediately after the current is enabled, the voltage on the isenxx pin is ignored for a period of time (t blank ) before enabling the current sense circuitry. this blanking time also sets the minimum on-time of the pwm cycle. advance information logic vm gate drive and ocp isen mode in3 in4 nsleep vm vm gate drive and ocp isen vm controller in1 in2 out2 out1 out4 out3 isen34 isen12 not connected
23 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated the pwm trip current is set by a comparator which compares the voltage across a current sense resistor connected to the isenxx pin with a reference voltage. this reference voltage (v trip ) is generated on-chip and decides the current trip level. the full-scale trip current in a winding is calculated as shown in equation 1 . where ? i trip is the regulated current. ? v trip is the internally generated trip voltage. ? r sensexx is the resistance of the sense resistor. ? torque is the torque scalar, the value of which depends on the input on trq pin. trq = 100% for trq pin connected to gnd (drv8847) or trq bit set to 0 (drv8847s) and trq = 50% connected to v ext (drv8847) or trq bit set to 1 (drv8847s). (1) for example, if the v trip voltage is 150 mv and the value of the sense resistor is 150 m , the full-scale trip current is 1 a (150 mv / (150 m ) = 1 a). note if current control is not needed, connect the isenxx pins directly to ground. 7.3.5 current recirculation and decay modes during pwm current trip operation, the h-bridge is enabled to drive current through the motor winding until the trip threshold of the current regulation is reached. after the trip current threshold is reached, the drive current is interrupted, but, because of the inductive nature of the motor, current must continue to flow for some time. this continuous flow of current is called recirculation current. a mixed decay allows a better current regulation by optimizing the current ripple by using fast and slow decay. mixed decay is a combination of fast and slow decay modes. in fast decay mode, the anti-parallel diodes of the opposite fets are conducting on to let the current decay faster as shown in figure 14 (see case 2). in slow decay mode, winding current is recirculated by enabling both low-side fets in the bridge (see case 3 in figure 14 ). mixed decay starts with fast decay, then goes to slow decay. in the drv8847 device, the mixed decay ratio is 25% fast decay and 75% slow decay as shown in figure 15 . figure 14. decay modes trip trip sensexx v i torque r advance information vm 1 drive current fast decay slow decay 1 2 2 3 3
24 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 15. mixed decay 7.3.6 torque scalar the torque scalar is used to dynamically adjust the output current through a digital input pin, trq. this torque scalar decreases the trip reference value of the output current to 50% (whenever the trq pin is pulled high). torque scalar can be used to scale the holding torque of the stepper motor. for the i 2 c device variant (drv8847s), this feature is implemented through an i 2 c register. when the trq pin is pulled-low (or the trq bit is reset in the drv8847s device variant), then trip current is calculated using equation 2 . (2) when the trq pin is pulled-high (or the trq bit is set in the drv8847s device variant), then trip current is calculated using equation 3 . (3) trip trip sensexx v i 0.5 r trip trip sensexx torque v i r u i trip t off 25% of t off t on mixed decay (25% fast decay) fast decay slow decay time motor current advance information
25 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7 stepping modes the drv8847 device is used to drive a stepper motor in full-stepping mode or non-circulating half-stepping mode using the following bridge configurations: ? full-stepping mode (with or without current regulation) ? using 4-pin interface configuration ? using 2-pin interface configuration ? half-stepping mode (with or without current regulation) ? using 4-pin interface configuration 7.3.7.1 full-stepping mode (4-pin interface) in full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase shift of 90 between the two windings. in 4-pin interface, the pwm input is applied to the in1, in2, in3, and in4 pins as shown in figure 16 and the driver operates only in forward (frw) and reverse (rev) mode. figure 16. full-stepping mode using 4-pin interface 90 o phase in1 in2 in3 in4 out12 frw out12 frw out12 rev out12 rev out34 frw out34 frw out34 rev out34 rev out12 out34 time advance information
26 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7.2 full-stepping mode (2-pin interface) in full-stepping using the 2-pin interface, the pwm input is only applied to the in1 and in2 pins, and the in3 is connected to ground (see the figure 11 section). figure 17 shows the full-stepping mode of stepper motor using the 2-pin interface figure 17. full-stepping mode using 2-pin interface 90 o phase in1 in2 out12 frw out12 frw out12 rev out12 rev out34 frw out34 frw out34 rev out34 rev out12 out34 time advance information
27 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.7.3 half-stepping mode in half-stepping mode, the full-bridge operates in one of the three modes (forward, reverse, or coast mode) with a phase shift of 45 between the two windings. in 4-pin interface, the pwm input is connected to the in1, in2, in3, and in4 pins as shown in figure 18 , and the driver operates in forward, reverse, and coast mode. figure 18. half-stepping mode using 4-pin interface advance information 45 o phase in1 in2 in3 in4 out12 frw out12 frw out12 rev out12 rev out34 frw out34 frw out34 rev out34 rev out12 out34 coast coast coast coast coast coast coast coast coast time
28 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3.8 motor driver protection circuits the drv8847 device is protected against vm undervoltage, overcurrent, open load, and over temperature events. 7.3.8.1 overcurrent protection (ocp) the drv8847 is protected against overcurrent by overcurrent protection trip. the ocp circuit on each fet disables the current flow through the fet by removing the gate drive. if this overcurrent detection continues for longer than the ocp deglitch time (t ocp ), all fets in the h-bridge (or half-bridge in the independent interface) are disabled and the nfault pin is driven low. the drv8847 device stays disabled until the retry time t retry occurs whereas the drv8847s device has a programmable option for auto-retry or the latch mode. 7.3.8.1.1 ocp automatic retry (hardware device and software device (ocpr = 0b)) after an ocp event in this mode, the corresponding half-bridges, full-bridge, or both bridges (depending on the mode bits) are disabled and the nfault pin is driven low (see table 10 and table 11 ). the ocp and corresponding ocpx bits are latched high in the i 2 c registers (see the register map section). normal operation resumes automatically (motor driver operation and the nfault pin is released) after the t retry time elapses as shown in figure 19 . the ocp and ocpx bits remain latched until the t retry period expires. figure 19. ocp operation 7.3.8.1.2 ocp latch mode (software device (ocpr = 1b)) ocp latch mode is only available in the drv8847s device. after an ocp event, the corresponding half-bridges, full-bridge, or both bridges (depending on the mode bits) are disabled and the nfault pin is driven low. the ocp and corresponding ocpx bits are latched high in the i 2 c registers (see the register map section). normal operation continues (motor driver operation and the nfault pin is released) when the ocp condition is removed and a clear faults command is issued through the clr_flt bit. 7.3.8.2 thermal shutdown (tsd) if the die temperature exceeds thermal shutdown limits (t tsd ), all fets in the h-bridge are disabled and the nfault pin is driven low. after the die temperature decreases to a value within the specified limits, normal operation resumes automatically. the nfault pin is released after operation starts again. 7.3.8.3 vm undervoltage lockout (vm_uvlo) whenever the voltage on the vm pin falls below the uvlo falling threshold voltage, v uvlo , all circuitry in the device is disabled, and all internal logic is reset. operation continues when the v vm voltage rises above the uvlo rising threshold as shown in figure 20 . the nfault pin is driven low during an undervoltage condition and is released after operation starts again. advance information i ocp t retry t ocp overshoot due to ocp deglitch time (t ocp ) motor current time
29 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 20. vm uvlo operation 7.3.8.4 open load detection (old) an open load detection feature is also implemented in this device. this diagnostic test runs at device power up or when the drv8847 device comes out from sleep mode (rising edge on the nsleep pin). the old diagnostic test can run any time in the i 2 c variant device (drv8847s) using the oldod (old on demand) bit. the old implementation is done on the full-bridge and the half-bridge. in the drv8847 device, during an open- load condition, the half-bridges, full-bridge, or both bridges (depending on the mode pin) are always operating and the nfault pin is pulled low. the user must reset the power to release the nfault pin by doing the old sequence again. table 7 lists the different old scenarios for the drv8847 device. in the drv8847s device, the user can program the full-bridge or half-bridge to be in the operating mode or the hi-z state, whenever an open-load condition is detected by using the oldbo (old bridge operation) bit. moreover, the nfault signaling on the old bit can be disabled using the oldfd (old fault disable) bit. for detailed i 2 c register settings, see the register map section. table 8 lists the different old scenarios for the drv8847s device. note for accurate old operation, the user must ensure that the motor is stationary (or current in connected load becomes zero) before the open load on-demand command is executed. table 7. open load detection in drv8847 interface load type old bridge operation nfault 4-pin 2-pin full-bridge connected no yes no half-bridge connected no yes no bridge open yes yes yes one half-bridge open yes yes yes parallel bridge full-bridge connected no yes no half-bridge connected no yes no bridge open yes yes yes one half-bridge open yes yes yes independent bridge full-bridge connected no yes no half-bridge connected no yes no bridge open yes yes yes one half-bridge open yes yes yes advance information v uvlo (min) falling v uvlo (max) falling v uvlo (max) rising v uvlo (min) rising v vm nfault device on device off device on time
30 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) the operation of the bridge is subjected to the selected mode type: ( a) in 4-pin or 2-pin interface, the corresponding bridge is in the operating or hi-z state. ( b) in parallel bridge (bdc) interface, both bridges are in the operating or hi-z state. ( c) in independent bridge interface, the corresponding half-bridge is in the operating or hi-z state. (2) depending on which half-bridge is open, the corresponding bit in the i 2 c register is set. table 8. open load detection in drv8847s (full-bridge-12) interface load type old bridge operation (1) nfault old bits oldbo = 0b oldbo = 1b old1 old2 old3 old4 4-pin 2-pin full-bridge connected no yes yes no 0b 0b x x half-bridge connected no yes yes no 0b 0b x x bridge open yes yes no yes 1b 1b x x one half-bridge open yes yes no yes 1b or 0b (2) 0b or 1b x x parallel bridge full-bridge connected no yes yes no 0b 0b x x half-bridge connected no yes yes no 0b 0b x x bridge open yes yes no yes 1b 1b x x one half-bridge open yes yes no yes 1b or 0b 0b or 1b x x independent bridge full-bridge connected no yes yes no 0b 0b x x half-bridge connected no yes yes no 0b 0b x x bridge open yes yes no yes 1b 1b x x one half-bridge open yes yes no yes 1b or 0b 0b or 1b x x as shown in figure 21 , during device wakeup, a constant current source pulls the out1 pin to the vdd voltage. if the voltage on the out2 pin is sensed to be less than the logic-low output voltage (v ol ), then an open-load condition is reported by pulling the nfault pin low. this test executes before the t wake or t on time has elapsed. when an open load is detected, the nfault pin is latched low until the device is power cycled. a similar implementation is done for the out3 and out4 pins. advance information
31 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 21. open load detect circuit 7.4 device functional modes the drv8847 device is active until the nsleep pin is pulled logic low. in sleep mode, the internal circuitry (charge pump and regulators) is disabled and all internal fets are disabled (hi-z state). note the t sleep time must elapse before the device goes to sleep mode. the device goes to operating mode automatically if the nsleep pin is pulled logic high. t wake must elapse before the device is ready for inputs. various functional modes are described in table 9 . the drv8847 device goes to a fault mode in the event of vm undervoltage (uvlo), overcurrent (ocp), open- load detection (old), and thermal shutdown (tsd). the functionality of each fault depends on the type of fault listed in table 10 for the drv8847 device and table 11 for the drv8847s device. advance information vm out2 out1 stepper motor dc motor + + 1 v 2.4 v old1 vdd vm + + 1 v 2.4 v old2 vdd sw sw to out3 and out4 x xx x
32 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated table 9. functional modes mode condition h-bridge internal circuits operating 2.7 v < v vm < 18 v nsleep pin = 1 operating operating sleep 2.7 v < v vm < 18 v nsleep pin = 0 disabled disabled fault any fault condition met depends on fault depends on fault table 10. fault support for drv8847 fault interface condition report h-bridge internal circuits recovery vm undervoltage (vm_uvlo) all interfaces vm < v uvlo nfault both h-bridges in hi-z state shutdown automatic: vm > v uvlo overcurrent (ocp) 4-pin 2-pin i > i ocp nfault corresponding h- bridges in hi-z state operating automatic: t retry parallel bridge both h-bridges in hi-z state independent bridge corresponding half-bridges in hi- z state open load detect (old) 4-pin full-bridge open nfault h-bridge in operating mode operating power cycle /reset: outx connected 2-pin parallel bridge full-bridges open nfault both h-bridges in operating mode independent bridge half-bridge open nfault half-bridge in operating mode thermal shutdown (tsd) all interfaces t j > t tsd (min 150 c) nfault both h-bridges in hi-z state operating t j < t tsd (t hys typ 40 c) (1) the state of the bridge in old is dependent on the oldbo bit as listed in table 16 . table 11. fault support for drv8847s fault mode condition report h-bridge internal circuits recovery vm undervoltage (vm_uvlo) all interfaces vm < v uvlo nfault both h-bridges in hi-z state shutdown automatic: vm > v uvlo overcurrent (ocp) 4-pin 2-pin i > i ocp nfault corresponding h- bridges in hi-z state operating automatic: t retry parallel bridge both h-bridges in hi-z state independent bridge interface corresponding half-bridges in hi- z state open load detect (old) 4-pin full-bridge open nfault h-bridge in operating or hi-z state (1) operating power cycle / reset: outx connected 2-pin parallel bridge full-bridges open nfault both h-bridges in operating or hi-z state independent bridge half-bridge open nfault half-bridge in operating or hi-z state thermal shutdown (tsd) all interfaces t j > t tsd (min 150 c) nfault both h-bridges in hi-z state operating t j < t tsd (t hys typ 40 c) advance information
33 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5 programming this section applies only to the drv88847s device (i 2 c variant). 7.5.1 i 2 c communication 7.5.1.1 i 2 c write to write on the i2c bus, the master device sends a start condition on the bus with the address of the 7-bit slave device. also, the last bit (the r/w bit) is set to 0b, which signifies a write. after the slave sends the acknowledge bit, the master device then sends the register address of the register to be written. the slave device sends an acknowledge (ack) signal again which notifies the master device that the slave device is ready. after this process, the master device sends 8-bit write data and terminates the transmission with a stop condition. figure 22. i 2 c write sequence 7.5.1.2 i 2 c read to read from a slave device, the master device must first communicate to the slave device which register will be read from. this communication is done by the master starting the transmission similarly to the write process which is by setting the address with the r/w bit equal to 0b (signifying a write). the master device then sends the register address of the register to be read from. when the slave device acknowledges this register address, the master device sends a start condition again, followed by the slave address with the r/w bit set to 1b (signifying a read). after this process, the slave device acknowledges the read request and the master device releases the sda bus, but continues supplying the clock to the slave device. during this part of the transaction, the master device becomes the master-receiver, and the slave device becomes the slave-transmitter. the master device continues sending out the clock pulses, but releases the sda line so that the slave device can transmit data. at the end of the byte, the master device send a negative- acknowledge (nack) signal, signaling to the slave device to stop communications and release the bus. the master device then sends a stop condition. figure 23. i 2 c read sequence start 7-bit slave address 8-bit data stop write to memory ack ack 8-bit register address ack r/w=0 start 7-bit slave address 7-bit slave address rstrt repeated start ack ack 8-bit register address ack r/w=0 r/w=1 8-bit data nack stop advance information
34 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated programming (continued) 7.5.2 multi-slave operation multi-slave operation is used to control multiple drv8847s devices through one i 2 c line as shown in figure 24 . the default device address of the drv8847 device is 0x60 (7-bit address). therefore, any drv8847s device can be accessed using this address. the steps for multi-slave configuration for programming device-1 out of 4 connected devices (as shown in figure 24 ) are as follows: figure 24. multi-slave operation of drv8847s ? the drv8847s device variant is configured for multi-slave operation by writing the disflt bit (ic2_con register) of all connected devices to 1b. this step will disable the nfault output pin of all drv8847s, to avoid any race condition between master and slave i 2 c device. ? pull the nfault pins (nfault2, nafult3, and nfault4 pins) of three devices (2, 3, and 4) to low to release the i 2 c buses of the slave device (device-2, device-3 and device-4). now only device-1 is connected to master. ? since, only one device, drv8847s (1), is connected to the controller, and, therefore, its slave address can be reprogrammed from default 0x60 (7-bit address) to another unique address. ? similarly, the slave address (slave_addr) of the other three devices (device-2, device-3 and device-4) can be reprogrammed sequentially to unique addresses by a combination of nfault pins. ? when all slave addresses are reprogrammed, resume the disflt bit to 0b (ic2_con register). this will enable the nfault output pin for fault flagging. ? all the nfault pins are released and a multi-slave setup is complete. now all connected slave devices can be accessed using the newly reprogrammed address. ? the above steps should be repeated for any device in case of a power reset (nsleep). . microcontroller (master) nfault (1) sda scl nfault (2) sda scl nfault (3) sda scl nfault (4) sda scl nfault1 nfault2 nfault4 nfault3 scl sda drv8847s (1) (slave 1) drv8847s (2) (slave 2) drv8847s (3) (slave 3) drv8847s (4) (slave 4) advance information
drv8847 www.ti.com slvse65 ? july 2018 35 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6 register map table 12 lists the memory-mapped i 2 c registers for the drv8847 device. the i 2 c registers are used to configure the drv8847s device and for device diagnostics. note do not modify reserved registers or addresses not listed in the register map ( table 12 ). writing to these registers may have unintended effects. for all reserved bits, the default value is 0b. table 12. i 2 c registers address acronym register name 7 6 5 4 3 2 1 0 access section 0x00 slave_addr slave address rsvd slave_addr rw go 0x01 ic1_con ic1 control trq in4 in3 in2 in1 i2cbc mode rw go 0x02 ic2_con ic2 control clrflt disflt rsvd decay ocpr oldod oldfd oldbo rw go 0x03 slr_status1 slew rate and fault status-1 rsvd slr rsvd nfault ocp old tsdf uvlof rw go 0x04 status2 fault status-2 old4 old3 old2 old1 ocp4 ocp3 ocp2 ocp1 r go advance information
36 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated complex bit access types are encoded to fit into small table cells. table 13 shows the codes that are used for access types in this section. table 13. access type codes access type code description read type r r read write type w w write reset or default value - n value after reset or the default value 7.6.1 slave address register (address = 0x00) [reset = 0x60] slave address is shown in figure 25 and described in table 14 . figure 25. slave address register 7 6 5 4 3 2 1 0 rsvd slave_addr r-0b r/w-1100000b table 14. slave address register field descriptions bit field type reset description 7 rsvd r 0b reserved 6-0 slave_addr r/w 1100000b slave address (8 bit) the default value is 0x60 7.6.2 ic1 control register (address = 0x01) [reset = 0x00] ic1 control is shown in figure 26 and described in table 15 . figure 26. ic1 control register 7 6 5 4 3 2 1 0 trq in4 in3 in2 in1 i2cbc mode r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-00b table 15. ic1 control register field descriptions bit field type reset description 7 trq r/w 0b 0b = torque scalar set to 100% 1b = torque scalar set to 50% 6 in4 r/w 0b the inx bits are used to control the bridge operation. 5 in3 r/w 0b the inx bits are used to control the bridge operation. 4 in2 r/w 0b the inx bits are used to control the bridge operation. 3 in1 r/w 0b the inx bits are used to control the bridge operation. 2 i2cbc r/w 0b 0b = bridge control configured by using the inx pins 1b = bridge control configured by using the inx bits 1-0 mode r/w 00b 00b = 4-pin interface 01b = 2-pin interface 10b = parallel interface 11b = independent mode advance information
37 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.3 ic2 control register (address = 0x02) [reset = 0x00] ic2 control is shown in figure 27 and described in table 16 . figure 27. ic2 control register 7 6 5 4 3 2 1 0 clrflt disflt rsvd decay ocpr oldod oldfd oldbo r/w-0b r/w-0b r-0b r/w-0b r/w-0b r/w-0b r/w-0b r/w-0b table 16. ic2 control register field descriptions bit field type reset description 7 clrflt r/w 0b set this bit to issue a clear fault command. this command clears all fault bits other than the old and oldx bits. this bit reset to 0b after clearing all the faults. 0b = no clear fault command issued 1b = clear fault command issued 6 disflt r/w 0b 0b = nfault pin not disable 1b = nfault pin is disabled 5 rsvd r 0b reserved 4 decay r/w 0b 0b = 25% fast decay 1b = 100% slow decay 3 ocpr r/w 0b 0b = ocp auto retry mode 1b = ocp latch mode 2 oldod r/w 0b 0b = idle 1b = old on-demand is activated 1 oldfd r/w 0b 0b = fault signaling on old 1b = no fault signaling on old 0 oldbo r/w 0b 0b = bridge operating on old 1b = bridge hi-z on old note errata: in current silicon, the clr_flt does not reset to 0b after clearing all the faults. this will be fixed in next revision. advance information
38 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.4 slew-rate and fault status-1 register (address = 0x03) [reset = 0x40] fault status-1 is shown in figure 28 and described in table 17 . figure 28. fault status-1 register 7 6 5 4 3 2 1 0 rsvd slr rsvd nfault ocp old tsdf uvlof r-0b r/w-0b r-0b r-0b r-0b r-0b r-0b r-0b table 17. fault status-1 register field descriptions bit field type reset description 7 rsvd r 0b reserved 6 slr r/w 0b 0b = 150 ns 1b = 300 ns 5 rsvd r 0b reserved 4 nfault r 0b 0b = no fault detected (mirrors the nfault pin) 1b = fault detected 3 ocp r 0b 0b = no ocp detected 1b = ocp detected 2 old r 0b 0b = no open load detected 1b = open load detected 1 tsdf r 0b 0b = no tsd fault detected 1b = tsd fault detected 0 uvlof r 0b 0b = no uvlo fault detected 1b = uvlo fault detected advance information
39 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6.5 fault status-2 register (address = 0x04) [reset = 0x00] fault status-2 is shown in figure 29 and described in table 18 . figure 29. fault status-2 register 7 6 5 4 3 2 1 0 old4 old3 old2 old1 ocp4 ocp3 ocp2 ocp1 r-0b r-0b r-0b r-0b r-0b r-0b r-0b r-0b table 18. fault status-2 register field descriptions bit field type reset description 7 old4 r 0b 0b = no open load detected on out4 1b = open load detected on out4 6 old3 r 0b 0b = no open load detected on out3 1b = open load detected on out3 5 old2 r 0b 0b = no open load detected on out2 1b = open load detected on out2 4 old1 r 0b 0b = no open load detected on out1 1b = open load detected on out1 3 ocp4 r 0b 0b = no ocp detected on out4 1b = ocp detected on out4 2 ocp3 r 0b 0b = no ocp detected on out3 1b = ocp detected on out3 1 ocp2 r 0b 0b = no ocp detected on out2 1b = ocp detected on out2 0 ocp1 r 0b 0b = no ocp detected on out1 1b = ocp detected on out1 advance information
40 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the drv8847 device is used in applications for stepper or brushed dc motor control. 8.2 typical application the user can configure the drv8847 for stepper motor and dual bdc motor applications as described in this section. 8.2.1 stepper motor application figure 30 shows the typical application of the drv8847 device to drive a stepper motor. figure 30. typical application schematic of device driving stepper motor 8.2.1.1 design requirements table 19 lists design input parameters for system design. table 19. design parameters design parameter reference example value motor supply voltage v m 12 v motor winding resistance r l 34 ? /phase motor winding inductance l l 33 mh/phase motor rms current i rms 350 ma target trip current i trip 350 ma trip current reference voltage (internal voltage) v trip 150 mv drv8847 nsleep isen12 out2 out4 isen34 out1 out3 nfault (logic supply) 1 3 4 5 6 2 7 8 in1 mode gnd vm trq in2 in4 in3 16 14 13 12 11 15 10 9 v ext stepper motor 330 m 330 m 10 f 0.1 f to controller advance information
41 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.1.2 detailed design procedure 8.2.1.2.1 current regulation the trip current (i trip ) is the maximum current driven through either winding. the amount of this current depends on the sense resistor value (r sensexx ) as shown in equation 4 (considering torque setting (trq) as 100%). (4) the i trip current is set by a comparator which compares the voltage across the r sensexx resistor to a reference voltage. to avoid saturation of the motor, the i trip current must be calculated as shown in equation 5 . where ? v vm is the motor supply voltage. ? r l is the motor winding resistance. ? r ds(on)_hs and r ds(on)_ls are the high-side and low-side on-state resistance of the fet. (5) for an i trip value of 350 ma, the value of the sense resistor (r sensexx ) is calculated as shown in equation 6 . (6) select the closest available value of 440 m for the sense resistors. selecting this value will effect the current accuracy by 2.8%. trip trip sensexx torque v i r u vm trip l ds(on) _ hs ds(on) _ ls sensexx v i r ( ) r ( ) r ( ) r ( ) : : : : advance information trip sense12 sense34 trip v 150 mv r r 428.6 m i 350 ma :
42 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2 dual bdc motor application figure 31 shows the typical application of drv8847 device to drive dual bdc motors. figure 31. typical application schematic of device driving two bdc motors 8.2.2.1 design requirements table 20 lists the design input parameters for system design. table 20. design parameters design parameter reference example value motor supply voltage v m 12 v motor winding resistance r l 13.2 ? motor winding inductance l l 500 h motor rms current i rms 490 ma motor start-up current i start 900 ma target trip current i trip 1.2 a trip current reference voltage (internal voltage) v trip 150 mv 8.2.2.2 detailed design procedure 8.2.2.2.1 motor voltage the motor voltage used in an application depends on the rating of the selected motor and the desired revolutions per minute (rpm). a higher voltage spins a brushed dc motor faster with the same pwm duty cycle applied to the power fets. a higher voltage also increases the rate of current change through the inductive motor windings. 8.2.2.2.2 current regulation the trip current (i trip ) is the maximum current driven through either winding. because the peak current (start current) of the motor is 900 ma, the i trip current level is selected to be just greater than the peak current. the selected i trip value for this example is 1.2 a. therefore, use equation 7 to select the value of the sense resistors (r sense12 and r sense34 ) connected to the isen12 and isen34 pins. (7) trip sense12 sense34 trip v 150 mv r r 125 m i 1.2 a : advance information bdc drv8847 nsleep isen12 out2 out4 isen34 out1 out3 nfault (logic supply) 1 3 4 5 6 2 7 8 in1 mode gnd vm trq in2 in4 in3 16 14 13 12 11 15 10 9 v ext bdc 330 m 330 m 10 f 0.1 f to controller
43 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.2.2.2.3 sense resistor for optimal performance, the sense resistor must: ? be a surface mount component ? have low inductance ? be rated for high enough power ? be placed closely to the motor driver the power dissipated by the sense resistor equals i rms 2 r. in this example, the peak current is 900 ma, the rms motor current is 490 ma, and the sense resistor value is 125 m . therefore, the sense resistors (r sense12 and r sense34 ) dissipate 30 mw (490 ma 2 125 m = 30 mw). the power quickly increases with higher current levels. resistors typically have a rated power within some ambient temperature range, along with a derated power curve for high ambient temperatures. when a printed circuit board (pcb) is shared with other components generating heat, margin should be added. for best practice, measure the actual sense resistor temperature in a final system, along with the power mosfets, because those components are often the hottest. because power resistors are larger and more expensive than standard resistors, the common practice is to use multiple standard resistors in parallel, between the sense node and ground. this practice distributes the current and heat dissipation. advance information
44 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 power supply recommendations the drv8847 device is designed to operate from an input voltage supply (v vm ) range from 2.7 v to 18 v. place a 0.1- f ceramic capacitor rated for vm as close to the drv8847 device as possible. in addition, a bulk capacitor with a value of at least 10 f must be included on the vm pin. 9.1 bulk capacitance sizing bulk capacitance sizing is an important factor in motor drive system design. the amount of bulk capacitance depends on a variety of factors including: ? type of power supply ? acceptable supply voltage ripple ? parasitic inductance in the power supply wiring ? type of motor (brushed dc, brushless dc, stepper) ? motor start-up current ? motor braking method the inductance between the power supply and motor drive system limits the rate that current can change from the power supply. if the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. size the bulk capacitance to meet acceptable voltage ripple levels. the data sheet provides a recommended minimum value, but system-level testing is required to determine the appropriate-sized bulk capacitor. figure 32. setup of motor drive system with external power supply advance information local bulk capacitor parasitic wire inductance + motor driver power supply motor drive system vm gnd + ic bypass capacitor
45 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 layout 10.1 layout guidelines bypass the vm pin to ground using a low-esr ceramic bypass capacitor with a recommended value of 10 f and rated for vm. place this capacitor as close to the vm pin as possible with a thick trace or ground plane connection to the device gnd pin. 10.2 layout example figure 33. layout recommendation of 16-pin tssop package for single-layer board figure 34. layout recommendation of 16-pin htssop package for double-layer board nsleep aisen aout2 bout2 bisen aout1 bout1 nfault 4 5 6 7 8 16 14 13 12 11 15 10 9 nsleep isen12 out2 out4 isen34 out1 out3 nfault in1 mode gnd vm trq in2 in4 in3 advance information 4 5 6 7 8 16 14 13 12 11 15 10 in3 nsleep isen12 out2 out4 sen34 out1 bout3 nfault in1 mode gnd vm trq in2 in4 in3
46 drv8847 slvse65 ? july 2018 www.ti.com product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 10.3 thermal considerations 10.3.1 maximum output current in actual operation, the maximum output current that is achievable with a motor driver is a function of the die temperature. this die temperature is greatly affected by ambient temperature and pcb design. essentially, the maximum motor current is the amount of current that results in a power dissipation level that, along with the thermal resistance of the package and pcb, keeps the die at a low enough temperature to avoid thermal shutdown. the dissipation ratings given in the data sheet can be used as a guide to calculate the approximate maximum power dissipation that can be expected without putting the device in thermal shutdown for several different pcb constructions. however, for accurate data, the actual pcb design must be analyzed through measurement or thermal simulation. 10.3.2 thermal protection the drv8847 device has thermal shutdown (tsd) as described in the maximum output current section. if the die temperature exceeds approximately 150 c, the device is disabled until the temperature deceases 40 c. any tendency of the device to enter tsd is an indication of either excessive power dissipation, insufficient heat- sinking, or too high an ambient temperature. 10.4 power dissipation power dissipation in the drv8847 device is dominated by the dc power dissipated in the output fet resistance (r ds(on)_hs and r ds(on)_ls ). additional power is dissipated because of pwm switching losses. these losses are dependent on the pwm frequency, rise and fall times, and vm supply voltages. these switching losses are typically on the order of 10% to 30% of the dc power dissipation. use equation 8 to estimate the dc power dissipation of one h-bridge. where ? p tot is the total power dissipation ? i out(rms) is the rms output current being applied to motor ? r ds(on)_hs and r ds(on)_ls are the high-side and low-side on-state resistance of the fet (8) note the value of r ds(on)_hs and r ds(on)_ls increases with temperature. therefore, as the device heats, the power dissipation increases. this relationship must be considered when sizing the heat-sink. 2 2 tot ds(on) _ls out(rms) ds(on) _hs out(rms) p r i r i u u advance information
47 drv8847 www.ti.com slvse65 ? july 2018 product folder links: drv8847 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? texas instruments, drv8847evm user ' s guide ? texas instruments, drv8847evm and drv8847sevm software user ' s guide ? texas instruments, small motors in large appliances ti technote 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks powerpad, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 1-sep-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples drv8847pwpr preview htssop pwp 16 2000 tbd call ti call ti -40 to 125 pdrv8847pwpr active htssop pwp 16 2000 tbd call ti call ti -40 to 125 PDRV8847SPWR active tssop pw 16 2000 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 1-sep-2018 addendum-page 2

www.ti.com package outline c 14x 0.65 2x 4.55 16x 0.30 0.19 typ 6.6 6.2 1.2 max 0.15 0.05 0.25 gage plane -8 0 b note 4 4.5 4.3 a note 3 5.1 4.9 0.75 0.50 (0.15) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 1 8 9 16 0.1 c a b pin 1 index area see detail a 0.1 c notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm per side. 5. reference jedec registration mo-153. seating plane a 20 detail a typical scale 2.500
www.ti.com example board layout 0.05 max all around 0.05 min all around 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. land pattern example exposed metal shown scale: 10x symm symm 1 8 9 16 15.000 metal solder mask opening metal under solder mask solder mask opening exposed metal exposed metal solder mask details non-solder mask defined (preferred) solder mask defined
www.ti.com example stencil design 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale: 10x symm symm 1 8 9 16

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